digital filter blocks (CIC, reset domain crossing (RDC), clock domain crossing (CDC), static timing analysis (STA), IIR), Verilog, RTL-to-GDSII design flow, Synthesis, synchronizers, arbitration logic, systemverilog, Pipelines, handshaking, digital RTL design, FIFOs, Fsms, mixed-signal design concepts, FIR

C++, Perl, Python, RTL Verilog, Uvm, systemverilog, SVA

Unix, Makefile, Configuration Management, Shell, PERL, System Verilog, Python, ARM CPU, PCI Express, verification dashboarding tools, Uvm, AMBA bus protocols, Ethernet bus protocols

Shell, Perl, Python, Tcl, Test Cases, Cadence Xcelium, Mentor QuestaSim, Synopsys VCS, Constrained Random Verification, Functional Verification, PCI Express PCIe protocol, ASIC SoC Design Verification, Functional Coverage Models, Verification Plans, Waveform analysis, Assertion-Based Verification SVA, Simulation Tools, SystemVerilog UVM, Testbenches, Assertions

Fpga, Usb, Perl, Pcie, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, MIPI, formal verification, Test Bench, transaction level modeling, AXI4

Shell, Perl, Verilog, Python, Tcl, Functional and code coverage, Simulation and debugging concepts, Automation scripts, Assertions SVA, UVM methodology, systemverilog

Perl, Verilog, Shell scripting, System Verilog, Python, test bench development, coverage assertion writing, Uvm

Pcie, Perl, Vcs, Ethernet, Python, Tcl, Verdi, Uvm, systemverilog