Unix, Shell, C, Linux, Perl, Verilog, Python, Uvm, systemverilog

Git, Bitbucket, Verilog, Visualstudio, Python, System C, Uvm, systemverilog

static timing analysis, EDA tools for synthesis, VHDL, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, low-power design techniques, digital IC ASIC design, RTL quality tools such as Spyglass Lint CDC RDC

UVM methodology, assertion-based verification, functional code coverage, protocol checkers VIPs, systemverilog, coverage-driven verification, PCIe Gen 3 4 5 6 protocol verification, AMBA protocols AXI AHB

regulators , Verilog, Matlab, IC design CAD tools, RF and Analog Design, Mixed signal circuits, TX, Bandgap bias circuits, RX, Spice, ADCs, Silicon Germanium SiGe BiCMOS, Spectre, Pll, DACs, HSIM, Filters, Bipolar Complementary Metal Oxide Semiconductor technology

Shell, Pcie, Perl, Arm, Python, Tcl, MCU, AMBA, Axi, UCIe, systemverilog