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Job Title: Verification Design Engineer (PCIe Gen 3/4/5/6)
Location: Bangalore
Company: Silicon Patterns
Experience: 7+ Years
Notice Period: Immediate to 60 Days
Job Overview
Silicon Patterns is looking for a highly skilled Verification Design Engineer with strong expertise in PCIe (Gen 3/4/5/6) protocols. The ideal candidate will have significant experience in advanced verification methodologies and SoC/IP verification.
Key Responsibilities
Required Skills & Qualifications
Preferred Qualifications
Why Join Silicon Patterns
Interested candidates can share their CV at:
[Confidential Information]
Job ID: 148488825
Skills:
Unix, Shell, C, Linux, Perl, Verilog, Python, Uvm, systemverilog
Skills:
C, Verilog, Verdi, Xcellium, JasperGold, systemverilog
Skills:
static timing analysis, LINT, Logic Synthesis, Dft, cdc, formal verification, Cadence-based ASIC design environments, low-power design methodologies, micro-architecture development, SystemVerilog RTL design
Skills:
scoreboard , Verilog, System Verilog, Verification Plan, UVM Environment, Test Benches, AMBA protocols, Uvm, Assertions, Functional coverage coding, DDR protocol knowledge, Axi, RTL debugging, Code Coverage analysis, AHB
Skills:
Assertions SVA, SystemVerilog SV, Timing Constraints SDC, Uvm, Functional coverage, Verification, Physical Design PD, Rtl Design
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