routing, static timing analysis, physical design methodologies, place and route tools, floorplanning, Placement

synopsys tools , Perl, Tcl, SoC integration, high-speed designs, ICC2, Process Improvements, Physical Verification, flow automation, Floor Planning, Calibre, Innovus, Netlist2GDSII implementation, power grid design, Tk

power integrity , Chip-Package Co-Design, Physical Design, floorplanning, Bump Planning, Package Interface Design, Signal Integrity, EDA Tools, Package Design

Perl, Python, Tcl, OCV, primetime, Fusion Compiler, ICC2, SI Crosstalk, ECO flows, MMMC, Timing Closure, POCV, AOCV, Clock Tree Synthesis

Tcl, PERL, Cadence Innovus, Tk

redhawk , Tcl, Python, Perl, Scripting Languages, Tempus, manufacturing sign-off, multi-clock domain handling, advanced nodes, ASIC SoC physical design, PrimeClouser, Cadence Innovus, Timing Analysis, Physical Verification, EDA Tools, DFT insertion, Calibre, EM IR analysis, primetime, Signal Integrity, low-power design, Voltus, reliability checks, power analysis