Excel, Python, Ms Word

Unix, Lsf, Jenkins, Git, Shell, Linux, Verilog, Gitlab, Python, Tcl, Synthesis, cdc, Simulation, RTL, make, systemverilog, RDC, UGE, LINT, Low Power, Slurm

Numpy, Git, Pandas, Pytorch, Version Control Systems, Python, machine learning frameworks, OpenAI’s GPT models, Hugging Face, data processing libraries, prompt engineering

Python, PERL, Debugging, Silicon Validation, analog simulation, silicon bring-up, Analog Circuit Design, noise analysis, stability and compensation, CMOS technology, device mismatch and variation, virtuoso

Orchestration, C++, Data Structures, Data Security, Sql, Python

static timing analysis, Perl, Python, EDA tools for synthesis, LINT, cdc, digital design principles, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, RTL quality tools such as Spyglass, RDC, VHDL, low-power design techniques

Java, Oauth, Apis, Automated Testing, Sso, React, Typescript, Distributed Systems, Python, intelligent automation platforms, event-driven systems, platform engineering, LLM-powered applications, AI agents, authentication and authorization, cloud-native architectures, observability