Shell, C, Python, Tcl, Cadence Palladium, UVM simulation, RTL Verilog, Synopsys ZeBu, systemverilog

Perl, Shell scripting, Python, vManager, Xcelium, Cadence environments, JasperGold, UVM methodologies

Vcs, Pcie, Python, Tcl, Xcelium, Uvm, systemverilog, APB, Questa, SVA assertions, AHB, AXI4

Usb, Pcie, Perl, Verilog, Python, Makefiles, RTL Build flows, AMBA protocols, Debug architecture, Axi, SoC Clocks, SDCC, APB, RST, SOC design, AHB, System-Verilog

Perl, Python, Tcl, Physical Design, Sta, ASIC Implementation, EM, PDN, Ir, make

Tcl Scripting, Ovm, Unix Shell Scripting, DDR, Perl, Pcie, Verilog, System Verilog, CMOS logic design, IC chip design development flow process, Uvm, Circuit Analysis, CAE CAD tools, Axi, VHDL, Circuit Design, AHB, coverage assertion driven verification

Ksh, Java, PowerShell, Kafka, Jenkins, Git, Perl, Ansible, Shell scripting, Bash, Python, Azure DevOps, RPM packaging, Podman Containers

redhawk , Tcl Scripting, Python, timing reports, primetime, Fusion Compiler, floorplanning, CTS routing, Tempus, LEC, Cadence Innovus, Physical Verification, setup hold debugging, Voltus, tile block PnR, Calibre, Asic Physical Design, Optimisation, StarRC, Parasitic Extraction, Placement, Synopsys ICC2

Yaml, Google Cloud Platform, Perl, Ansible, Xml, Bash, Microsoft Azure, Json, Red Hat Enterprise Linux, Python, Red Hat Ansible Automation Platform