Pcie, Perl, Vcs, Ethernet, Python, Tcl, Verdi, Uvm, systemverilog

Usb, Mac, Pcie, Perl, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB

Jtag, Verilog, Integration, System Verilog, ATB-AMBA protocol, SoC development, Trace triggers, Uvm, Debug architecture, Gate Level simulations, verification testbench, Axi, Asic Design Verification, Crash flow, Power aware simulations, monitors, Validation, AHB, Scandump

code coverage , JIRA, Pcie, Shell scripting, Python, Arm Cortex, C++, Git, Perl, Ethernet, Tcl, Uvm, transaction-level modelling, constrained-random verification, SERDES, Cadence vManager, functional coverage, verification methodologies, O-RAN, gate-level simulation, systemverilog, AMBA, Axi, hardware software co-verification, AHB

Python, System Verilog, Systemc, Pcie, Hybrid test benches, MDV, DV signoffs, SV, CDV, Uvm, Simulation Scripts, test vectors, Coverage, Regression, UCIe, Axi, testplan creation, DV Infrastructure, building testbenches, stimulus based verification, SystemC based reference model