Shell, Perl, Python, Tcl, coverage-driven methodologies, Uvm, systemverilog, SVA, constrained-random verification

Test Planning, C, Systemc, Shell, Verilog, Tcl, Python, power-aware verification using UPF, systemverilog, NoC bus and interconnect verification, assertions, transaction-level modeling, UVM-based testbench development, constrained-random verification, formal verification

Verilog, Test Plan Creation, cdc, VHDL, RDC, Uvm, systemverilog, DV environments, Execution, APB bus protocols, block functional models, BFM, UPF, formal verification methodologies, constrained random verification techniques, CPF, AHB, low-power verification

Verilog, systemverilog, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, VMM, random stimulus

Pcie, Ovm, Scripting, System Verilog, Ethernet, Uvm, HBM2, HBM3, Memory protocols, GDDRx, SVA, AHB, LPDDR4, AMBA standards, APB, High speed SerDes, Axi

Perl, Vcs, Python, Tcl, Uvm, Verdi, Questa, systemverilog