power integrity , Automation, DDR, Pcie, Cadence, GDDR, AI-assisted design methodologies, High-speed interface IPs, Timing Closure, Physical Design, SERDES, EDA Tools, LPDDR, Synopsys, Signal Integrity

clock tree synthesis (CTS), Electromigration (EM) checks, Static Timing Analysis (STA), routing, Perl, Python, Tcl, floorplanning, Make-based automation scripts, Asic Physical Design, timing optimization, signoff, setup and hold timing analysis, LVS, Power Planning, Physical Verification, RTL-to-GDSII implementation, Timing Closure, DRC, Placement, constraint validation, power integrity analysis

power integrity , DDR, Pcie, Cadence, GDDR, High-speed interface IPs, Timing Closure, Physical Design, SERDES, EDA Tools, LPDDR, Synopsys, Signal Integrity

Tcl, Python, Perl, Innovus, Sign-off, Power Grid, SI crosstalk analysis, Tempus STA, ECO generation, pegasus, Calibre, floorplanning, CTS, Sta, MMMC, GDSII, Cadence Toolchain, Timing Closure

redhawk , Python, Perl, Integration, Tcl, primetime, Fusion Compiler, ICC2, package technologies, Asic Physical Design, Innovus, Calibre, C4, chip-level floorplanning, bump and RDL experience, full-chip tape-outs, timing power convergence, microbump, multi-voltage design, UCIe, interposer, Totem, 3D, low-power UPF, FCBGA, TSV, IR EM analysis, 2.5D

routing, Debugging, STA timing closure, Optimization, EM IR analysis and closure, Full-Chip Physical Design, Cadence Innovus, Physical Verification, Clock Tree Synthesis, Problem-solving

hardware engineering , Static Timing Analysis (STA), Automation, Deep sub-micron technology, Multi-voltage domains, Circuit Design, Power gating, UPF, Physical Design, Synthesis, ASIC design flows, Sign-off optimizations, PNR, device physics, Low power design implementation