Physical Design Lead
Physical Design Lead
best nanotech- Posted 3 days ago
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Job Description
We are looking for an experienced Physical Design Lead with 7–10 years of hands-on experience in ASIC Physical Design and implementation. The candidate should have strong expertise in end-to-end RTL-to-GDSII implementation, advanced technology nodes (7nm/5nm/3nm), timing closure, physical verification, and signoff. The role requires full-chip implementation and successful tapeout experience, along with 1–2 years of technical team leadership.
2. Key Responsibilities
- Lead end-to-end ASIC Physical Design implementation from floorplanning to GDSII signoff.
- Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and optimization.
- Drive Physical Design implementation at advanced technology nodes, preferably 7nm, 5nm, or 3nm.
- Execute Static Timing Analysis (STA), timing optimization, and timing closure across multiple corners and modes.
- Perform setup and hold timing analysis, constraint validation, and timing signoff.
- Manage physical verification activities, including DRC, LVS, and physical signoff.
- Perform power integrity analysis, including IR Drop and Electromigration (EM) checks.
- Work on full-chip and block-level Physical Design implementation.
- Support design integration, signoff closure, and successful ASIC tapeouts.
- Develop and maintain TCL, Python, Perl, and Make-based automation scripts.
- Lead and mentor Physical Design engineers, review implementation quality, and coordinate technical deliverables.
- Collaborate with RTL Design, DFT, STA, and Physical Verification teams to resolve implementation and signoff issues.
3. Required Qualifications
- Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Microelectronics, or a related discipline.
- 7–10 years of hands-on experience in ASIC Physical Design.
- 1–2 years of team handling or technical leadership experience.
- Strong understanding of semiconductor design methodologies and RTL-to-GDSII implementation.
- Hands-on experience with advanced technology nodes, preferably 7nm/5nm/3nm.
- Demonstrated experience in full-chip implementation and successful tapeouts.
- Strong understanding of Physical Design signoff requirements and timing closure.
More Info
Key Skills
clock tree synthesis (CTS)
Make-based automation scripts
timing optimization
signoff
setup and hold timing analysis
RTL-to-GDSII implementation
DRC
Electromigration (EM) checks
constraint validation
Static Timing Analysis (STA)
power integrity analysis
About Company
Skills:
power integrity , Automation, DDR, Pcie, Cadence, GDDR, AI-assisted design methodologies, High-speed interface IPs, Timing Closure, Physical Design, SERDES, EDA Tools, LPDDR, Synopsys, Signal Integrity
Skills:
power integrity , DDR, Pcie, Cadence, GDDR, High-speed interface IPs, Timing Closure, Physical Design, SERDES, EDA Tools, LPDDR, Synopsys, Signal Integrity
Skills:
power integrity , Static Timing Analysis, Python, Pvs, Tcl, floorplanning, IR-drop, EM, LVS, Dfm, Place-and-Route, Physical Verification, Thermal-aware Placement, Physical Design, Timing Closure, ERC, DRC, UCIe PHY Integration, Antenna, Calibre, primetime, StarRC, ICC2, Synopsys Fusion Compiler, Cadence Innovus
Skills:
Tcl, Python, Perl, Innovus, Sign-off, Power Grid, SI crosstalk analysis, Tempus STA, ECO generation, pegasus, Calibre, floorplanning, CTS, Sta, MMMC, GDSII, Cadence Toolchain, Timing Closure
Skills:
redhawk , Python, Routing, Apache, Perl, Tcl, physical design methodologies, floor-planning, CTS, LVS, PPA tradeoffs, Calibre, Physical Verification, Extraction, StarRC, Synopsys fusion compiler, floor plan synthesis, Synthesis, CPU physical design, EM, Ir, signoff, Place And Route, Timing Closure, DRC, Placement, Cadence PrimeTime