bandwidth management , Universal Verification Methodology (UVM), Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, Specman E, hierarchical memory subsystems, Debug, IP subsystem SoCs, congestion control, regression systems, systemverilog, vector processing units, revision control systems, packet processing, AI ML Accelerators, constrained-random verification environments, Verification

Usb, Mac, Pcie, Perl, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB

Networking, Pcie, Test Methodologies, Ethernet, Axi, AMBA

Tcl Scripting, Unix Shell Scripting, Perl, Verilog, System Verilog, Debugging, Incisive, IMC, analog mixed signal design, Uvm, advanced verification methodologies, xCelium, vManager, Cadence Virtuoso, test bench development, verification IP, object-oriented programming, Simulation, behavioral modelling, mixed signal verification environment, verification plans, analog blocks

Shell, Perl, Verilog, Python, Tcl, Functional and code coverage, Simulation and debugging concepts, Automation scripts, Assertions SVA, UVM methodology, systemverilog

Pcie, Perl, Vcs, Ethernet, Python, Tcl, Verdi, Uvm, systemverilog

Ovm, Debugging, Test Planning, CHI, SoC design verification, AMBA protocols, Uvm, UVM-based test benches, system simulation tools, Axi, APB, emulation models, AHB