code coverage , Cpu, Usb, Oops, Verilog, Arm, Networking, Ethernet, Pcie, DDR, AHB, spyglass, LINT, SV, Graphics, SoC Verification, cdc, AMBA, RTL Coding, VHDL, C tests, SV METH, Axi

Usb, Mac, Pcie, Perl, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB

Jtag, Verilog, Integration, System Verilog, ATB-AMBA protocol, SoC development, Trace triggers, Uvm, Debug architecture, Gate Level simulations, verification testbench, Axi, Asic Design Verification, Crash flow, Power aware simulations, monitors, Validation, AHB, Scandump

Pcie, Perl, Vcs, Ethernet, Python, Tcl, Verdi, Uvm, systemverilog

Python, System Verilog, Systemc, Pcie, Hybrid test benches, MDV, DV signoffs, SV, CDV, Uvm, Simulation Scripts, test vectors, Coverage, Regression, UCIe, Axi, testplan creation, DV Infrastructure, building testbenches, stimulus based verification, SystemC based reference model