power integrity , Automation, DDR, Pcie, Cadence, GDDR, AI-assisted design methodologies, High-speed interface IPs, Timing Closure, Physical Design, SERDES, EDA Tools, LPDDR, Synopsys, Signal Integrity

power integrity , DDR, Pcie, Cadence, GDDR, High-speed interface IPs, Timing Closure, Physical Design, SERDES, EDA Tools, LPDDR, Synopsys, Signal Integrity

power integrity , Static Timing Analysis, Python, Pvs, Tcl, floorplanning, IR-drop, EM, LVS, Dfm, Place-and-Route, Physical Verification, Thermal-aware Placement, Physical Design, Timing Closure, ERC, DRC, UCIe PHY Integration, Antenna, Calibre, primetime, StarRC, ICC2, Synopsys Fusion Compiler, Cadence Innovus

Tcl, Python, Perl, Innovus, Sign-off, Power Grid, SI crosstalk analysis, Tempus STA, ECO generation, pegasus, Calibre, floorplanning, CTS, Sta, MMMC, GDSII, Cadence Toolchain, Timing Closure

redhawk , Python, Routing, Apache, Perl, Tcl, physical design methodologies, floor-planning, CTS, LVS, PPA tradeoffs, Calibre, Physical Verification, Extraction, StarRC, Synopsys fusion compiler, floor plan synthesis, Synthesis, CPU physical design, EM, Ir, signoff, Place And Route, Timing Closure, DRC, Placement, Cadence PrimeTime

Routing, Sta, CTS, floorplanning, EM, Ir, LVS, Physical Implementation, Synthesis, Physical Design, Placement, Si, DRC, RTL Netlist, Timing Closure, Tape-out, Power Domains, GDSII, Hierarchical Designs

redhawk , Python, Perl, Integration, Tcl, primetime, Fusion Compiler, ICC2, package technologies, Asic Physical Design, Innovus, Calibre, C4, chip-level floorplanning, bump and RDL experience, full-chip tape-outs, timing power convergence, microbump, multi-voltage design, UCIe, interposer, Totem, 3D, low-power UPF, FCBGA, TSV, IR EM analysis, 2.5D

routing, Debugging, STA timing closure, Optimization, EM IR analysis and closure, Full-Chip Physical Design, Cadence Innovus, Physical Verification, Clock Tree Synthesis, Problem-solving

hardware engineering , Perl Scripting, Sta, High Speed Cores, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Power Gating, High Frequency Design Convergence, PDN Methodology, PPA Targets, Timing Signoff