Physical Design Lead
- Posted a month ago
- Be among the first 10 applicants
Job Description
We are looking for an experienced Physical Design / SoC Full-Chip Technical Lead to drive the execution, methodology, and physical closure of complex next-generation SoC designs across advanced technology nodes, including 7nm, 5nm, 3nm, and beyond.
This role offers the opportunity to lead technically challenging full-chip implementations, collaborate closely with architecture and design teams, and own the physical implementation journey from RTL/Netlist to GDSII and tape-out.
Key Responsibilities
Technical Leadership & Full-Chip Ownership
- Lead end-to-end physical implementation of complex SoCs and large sub-systems from RTL/Netlist through GDSII and tape-out.
- Provide technical leadership and mentorship to the Physical Design team.
- Drive execution, schedules, methodologies, and technical deliverables across the full-chip implementation flow.
- Partner with Architecture, RTL, DFT, STA, Power, Signal Integrity, Packaging, and Verification teams to resolve complex design challenges.
What We're Looking For
- Strong experience in full-chip Physical Design / Physical Implementation of complex SoCs.
- Proven experience working on advanced process nodes such as 7nm, 5nm, 3nm, or below.
- Strong understanding of the complete RTL-to-GDSII flow.
- Hands-on expertise in Floorplanning, Synthesis, Placement, CTS, Routing, STA, SI, DRC/LVS, and EM/IR.
- Experience with hierarchical designs, large SoCs, complex power domains, and challenging timing closure.
- Strong problem-solving and technical leadership skills.
- Ability to work effectively across multiple engineering disciplines and drive issues to closure.
- Experience mentoring engineers and leading technical execution across complex projects.
Why Join Us
- Work on next-generation SoCs using advanced semiconductor process technologies.
- Solve challenging problems across physical implementation, timing, power, and signal integrity.
- Work with highly experienced cross-functional engineering teams.
- Opportunity to influence physical design methodologies, automation, and execution strategy.
- Play a key role in delivering complex designs from concept to successful tape-out.
More Info
Key Skills
CTS
EM
Physical Implementation
DRC
RTL Netlist
Tape-out
Power Domains
GDSII
Hierarchical Designs
About Company
Skills:
redhawk , Python, Routing, Apache, Perl, Tcl, physical design methodologies, floor-planning, CTS, PPA tradeoffs, LVS, Calibre, Physical Verification, Extraction, StarRC, Synopsys fusion compiler, floor plan synthesis, Synthesis, CPU physical design, EM, Ir, signoff, Place And Route, Timing Closure, DRC, Placement, Cadence PrimeTime
Skills:
clock tree synthesis (CTS), Electromigration (EM) checks, Static Timing Analysis (STA), routing, Perl, Python, Tcl, floorplanning, Make-based automation scripts, Asic Physical Design, timing optimization, signoff, setup and hold timing analysis, LVS, Power Planning, Physical Verification, RTL-to-GDSII implementation, Timing Closure, DRC, Placement, constraint validation, power integrity analysis
Skills:
Tcl, Python, Perl, Innovus, Sign-off, Power Grid, SI crosstalk analysis, Tempus STA, ECO generation, pegasus, Calibre, floorplanning, CTS, Sta, MMMC, GDSII, Cadence Toolchain, Timing Closure
Skills:
redhawk , Python, Routing, Apache, Perl, Tcl, physical design methodologies, floor-planning, CTS, LVS, PPA tradeoffs, Calibre, Physical Verification, Extraction, StarRC, Synopsys fusion compiler, floor plan synthesis, Synthesis, CPU physical design, EM, Ir, signoff, Place And Route, Timing Closure, DRC, Placement, Cadence PrimeTime
Skills:
routing, Debugging, STA timing closure, Optimization, EM IR analysis and closure, Full-Chip Physical Design, Cadence Innovus, Physical Verification, Clock Tree Synthesis, Problem-solving