Search Jobs
Search by job, company or skills
Search by job, company or skills
Hi All,
ACL Digital is hiring Design Verification Engineers
Experience: 8+ years
Location: Hyderabad / Bangalore
Join: Immediate
Key Skills:
10+ Years in IP/Sub-System/SoC DV Testbench Development
Strong in SV UVM, Functional & Formal Verification
Hands-on with RISC-V / CPU / PCIe / DDR / Ethernet
SoC Integration, Debugging & Coverage Closure
Expertise in Assertions & Complex Verification Flows
Thanks,
K Himabindu
Job ID: 144750925
Skills:
Fpga, Perl, Python, object-oriented programming, RTL, test plan development, Uvm, emulation platforms, systemverilog, automation scripts
Skills:
Perl, Verilog, Python, Synopsys VCS, Cadence Incisive, VHDL, Modelsim, Uvm
Skills:
Debugging, Automated Test Scripts, Documentation, Design Verification, Functional Verification, Test Plan Development
Skills:
Shell, Perl, Python, Tcl, Assertions SVA, UVM methodology, Debugging RTL verification issues, Coverage-driven verification, systemverilog, Functional Verification
Skills:
Perl, Makefile, Ruby, Python, C-DPI, Axi, AMBA, ASIC verification tools, Uvm, AHB, systemverilog
We don’t charge any money for job offers
