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•5 Years of ASIC SoC Verification Experience
• Expertise in SV-UVM, C, Assertions coding
• Must have good understanding of ARM processor based SoC architecture and must have completed verification of two or more embedded processor based SoC
• Must have expertise in on ASIC verification methodologies and ASIC design flow.
• Have expertise on ARM based SOC software framework (multi-core multi-layer APIs)
• Proven experience of the design verification methodologies such as UVM, assertion based coverage driven verification (code & functional coverage), constraint random test generation
• Strong problem solving/debugging skills
• Experience on working in SOC with complex Analog-Digital Interface will be considered as advantage.
• Experience on working in SOC with WREAL/AMS model will be considered as advantage
• Experience in Scripting Languages like Perl, awk, sed, will be an advantage
Job ID: 116788413
Skills:
Perl, Verilog, Python, Synopsys VCS, Cadence Incisive, VHDL, Modelsim, Uvm
Skills:
Shell, Perl, Python, Tcl, Assertions SVA, UVM methodology, Debugging RTL verification issues, Coverage-driven verification, systemverilog, Functional Verification
Skills:
Perl, Makefile, Ruby, Python, C-DPI, Axi, AMBA, ASIC verification tools, Uvm, AHB, systemverilog
Skills:
Vcs, DDR, Shell, Pcie, Perl, Ethernet, Python, Verdi, CHI, IUS, Uvm, systemverilog, Axi, Questa, AHB
Skills:
Test Plan Creation, Debugging, Python, Perl, VIP integration, testbench architecture, Uvm, verification methodologies, scoreboarding, systemverilog, coverage-driven verification, execution and review, assertions, regression management, debug flows, functional coverage
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