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Experience - 7+years
Location - Pan India
NP - Immediate to 60 Days
JD Physical Design -
Job ID: 145164405
Skills:
redhawk , Tcl, Routing, Python, Perl, Multi-voltage domains, Foundry PDKs, UPF, Timing Closure, Signoff, Cadence Innovus, Power gating, floorplanning, primetime, Tempus, Synopsys ICC2, CPF, Voltus, Placement, Physical Design, Samsung, Low-power design techniques
Skills:
Debugging, Logic Design, Sta, Circuit Design, Physical Verification, PNR, Physical Design, EDA Tools, Optimization, Rtl Design
Skills:
redhawk , Perl, Python, Tcl, EMIR sign-off flows, Voltus, electromigration analysis, Totem, chip-package co-simulation, EMIR sign-off methodology, chip-package co-design, PDN planning, PDN architecture planning
Skills:
physical verification using ICV, Innovus, VLSI Physical Design flows, Fusion Compiler, Synopsys Cadence Physical Design tools
Skills:
Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology
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