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Senior Physical Design Engineer
Location- Bengaluru
Experience -5+years
About the Role
At our core, we build silicon that powers products used by millions worldwide. As a Senior Physical Design Engineer, you'll be part of a high‑impact team driving next‑generation SoC designs. You'll own critical blocks, push boundaries in performance, power, and area, and collaborate with global teams to deliver tape‑outs at advanced nodes. This is a role for engineers who thrive on solving complex problems and want to see their work make a global impact.
What You'll Do
Basic Qualifications
Preferred Qualifications
About Us:
LeadSoC Technologies offers cutting edge Engineering Design services in VLSI and Embedded Systems. We have been growing rapidly over the last 9+ years to meet the evolving needs of the Semiconductor, Automotive, Telecom and Consumer Electronics segments. Our End-to-End VLSI design services span Micro Architecture to Tape Out and beyond with Post Silicon support. We have been involved in co-development of multiple SOC releases for our clients. LeadSoC has in house VLSI labs equipped with state of art tools (from leading EDA OEM's) for grooming talent. We work on SOC's, FPGA and ASIC platforms in areas spanning Digital Front End Design & Verification, Back End Design (RTL=> GDS), Analog & Custom Design & Verification. We also work on RF & Board Design for OEMs. Our Software practice works in areas spanning Firmware design, Hardware Abstraction, Kernel Space & User space design. We work on both bare metal and RTOS/Linux like platforms across x86, ARM, MIPS & Power PC architectures across multiple chipsets. Our presence in Concept to Manufacturing, spans across a broad spectrum of capabilities including Board Design, Platform Software solutions (Boot Loader, Bare Metal Firmware, Drivers/BSP, Abstraction layers), Middleware (Stacks, Frameworks, diagnostics), Target application, HMI (industry standard frameworks), IoT and Cloud (AWS, GCP, Azure) applications and V&V services. We have an embedded Software COE with in-house Labs, powered by open-source tool chain equipped with variety of reference boards. This environment enables our engineers to play while they learn. It also creates an environment for the engineers to ideate / create reference Solutions, POC designs. Our teams have been involved in providing frameworks for On-board Diagnostics, Manufacturing diagnostics, Post & Pre-Silicon Validation and Performance Optimization for products based on Linux / RTOS platforms. We have also worked on migrating stacks from legacy to NextGen platforms.
Website
http://www.leadsoc.com
Job ID: 148301119
Skills:
redhawk , Tcl, Routing, Python, Perl, Multi-voltage domains, Foundry PDKs, UPF, Timing Closure, Signoff, Cadence Innovus, Power gating, floorplanning, primetime, Tempus, Synopsys ICC2, CPF, Voltus, Placement, Physical Design, Samsung, Low-power design techniques
Skills:
Debugging, Logic Design, Sta, Circuit Design, Physical Verification, PNR, Physical Design, EDA Tools, Optimization, Rtl Design
Skills:
static timing analysis, PVT conditions, timing budgeting, timing rollups, Timing Analysis, timing constraint adaptation, clock network optimization, timing models
Skills:
redhawk , Perl, Python, Tcl, EMIR sign-off flows, Voltus, electromigration analysis, Totem, chip-package co-simulation, EMIR sign-off methodology, chip-package co-design, PDN planning, PDN architecture planning
Skills:
Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology
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