Perl, Verilog, Python, Synopsys VCS, Cadence Incisive, VHDL, Modelsim, Uvm

Shell, Perl, Python, Tcl, Assertions SVA, UVM methodology, Debugging RTL verification issues, Coverage-driven verification, systemverilog, Functional Verification

Perl, Makefile, Ruby, Python, C-DPI, Axi, AMBA, ASIC verification tools, Uvm, AHB, systemverilog

Vcs, DDR, Shell, Pcie, Perl, Ethernet, Python, Verdi, CHI, IUS, Uvm, systemverilog, Axi, Questa, AHB

Python, Systemc, MDV, simulation scripts, hybrid testbenches, regression systems, verification execution, Uvm, systemverilog, testbenches, CDV, coverage models

Mac, Pcie, Switches, Ethernet, FPGA verification, RDMA, NICs, SmartNICs, networking architectures, Uvm, systemverilog

Verilog, advanced stimulus generation techniques, Uvm, coverage-driven verification, systemverilog

Test Plan Creation, Debugging, Python, Perl, VIP integration, testbench architecture, Uvm, verification methodologies, scoreboarding, systemverilog, coverage-driven verification, execution and review, assertions, regression management, debug flows, functional coverage

Scripting Languages, Sed, Awk, Perl, ARM processor based SoC architecture, ASIC design flow, ASIC verification methodologies, C Assertions coding, multi-core multi-layer APIs, functional coverage, SV-UVM, constraint random test generation, UVM assertion based coverage driven verification, ARM based SOC software framework